RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v27]

[Vladimir Kozlov]

On Tue, 21 May 2024 23:57:34 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

>> Add instruction encoding support for Intel APX extended general-purpose registers:
>> 
>> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>> 
>> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.
>
> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
> 
>   add comment to ::stmxcsr and ::ldmxcsr

src/hotspot/cpu/x86/assembler_x86.cpp line 13030:

> 13028:     }
> 13029:   }
> 13030:   if (is_map1) emit_int8(0x0F);

- First. What `is_map1` means? There is no explanation for this name. May be add comment somewhere in `assembler_x86.hpp` file or use more meaningful name.

- Second. You added one more byte `0x0F` for instructions even when extended registers are not used and APX is not enabled. Why?  You added it in several `prefix()` and `prefixq()` methods. It can lead to regression since code size will increase.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1609089328