RFR: 8332615: RISC-V: Support vector unsigned comparison instructions for machines with RVV

[Fei Yang]

On Tue, 21 May 2024 14:19:52 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Hi, I noticed the following warning in the Opto JIT Code for the Vector API in the `test/jdk/jdk/incubator/vector/Int256VectorTests.java: UNSIGNED_LTInt256VectorTests` test:
> 
>   ** not supported: unsigned comparison op=comp/1 vlen=8 etype=int ismask=usestore
> ``` 
> After this Patch, We supports vector unsigned comparison instructions, the test passes normally and generates the Opto JIT Code such as:
> 
> 23e     B46: #  out( B48 B47 ) <- in( B25 B45 ) Loop( B46-B45 ) Freq: 955.829
> 23e     addw  R24, R29, zr  #@convI2L_reg_reg
> 242     slli  R30, R24, (#2 & 0x3f) #@lShiftL_reg_imm
> 246     add R17, R8, R30  # ptr, #@addP_reg_reg
> 24a     add R19, R9, R30  # ptr, #@addP_reg_reg
> 24e     addi  R30, R17, #16 # ptr, #@addP_reg_imm
> 252     addi  R31, R19, #16 # ptr, #@addP_reg_imm
> 256     loadV V1, [R30] # vector (rvv)
> 25e     loadV V2, [R31] # vector (rvv)
> 266     vmaskcmp V0, V1, V2, #19
> 272     vmask_tolong R20, V0
> 280     vstoremask V1, V0 # elem size is #4 byte[s]
> 28c     lw  R31, [R17, #16] # int, #@loadI
> 290     lw  R11, [R19, #16] # int, #@loadI
> 294     andi  R10, R20, #1  #@andL_reg_imm
> 298     bne  R10, zr, B48 #@cmpL_reg_imm0_branch  P=0.669978 C=14596.000000
> 
> ### Testing:
> qemu 8.1.50 with UseRVV:
> - [ ] Run tier1-3 tests (release)
> - [x] Run test/jdk/jdk/incubator/vector (fastdebug)

Looks good. Thanks!

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Marked as reviewed by fyang (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/19328#pullrequestreview-2070498642