RFR: 8320999: RISC-V: C2 RotateLeftV

[Ludovic Henry]

On Tue, 21 May 2024 11:51:00 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review this patch?
> More detailed description is inline in the code.
> Thanks

src/hotspot/cpu/riscv/assembler_riscv.hpp line 1887:

> 1885: 
> 1886:   // Vector Bit-manipulation used in Cryptography (Zvbb) Extension
> 1887:   INSN(vrol_vx,    0b1010111, 0b100, 0b010101);

we are not using `vrol_vx` anywhere.

src/hotspot/cpu/riscv/assembler_riscv.hpp line 1899:

> 1897: 
> 1898:   // Vector Bit-manipulation used in Cryptography (Zvbb) Extension
> 1899:   INSN(vror_vi,    0b1010111, 0b011, 0b010100);

I'm assuming there is not `vrol_vi`? It would be worth leaving a small comment here like

// There is no `vrol_vi` instruction.

src/hotspot/cpu/riscv/matcher_riscv.hpp line 132:

> 130:   // Does the CPU supports vector variable shift instructions?
> 131:   static constexpr bool supports_vector_variable_shifts(void) {
> 132:     return true;

What's the path to checking for `UseZvbb` and `UseZvbc` respectively to the specific instruction?

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PR Review Comment: https://git.openjdk.org/jdk/pull/19325#discussion_r1610063874
PR Review Comment: https://git.openjdk.org/jdk/pull/19325#discussion_r1610059606
PR Review Comment: https://git.openjdk.org/jdk/pull/19325#discussion_r1610046593