RFR: 8341146: RISC-V: Unnecessary fences used for load-acquire in template interpreter

[Feilong Jiang]

On Tue, 1 Oct 2024 17:57:53 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi, please consider.
>> 
>> RISC-V does not currently have plain load and store opcodes with aq or rl annotations, load-acquire and
>> store-release operations are implemented using fences instead. Initially, we followed the RISC-V spec
>> and placed FENCE RW,RW fence in front of load-acquire operation when porting the template interpreter.
>> The purpose is to enforce a store-release-to-load-acquire ordering (where there must be a FENCE RW,RW
>> between the store-release and load-acquire). But it turns out these fences are unnecessary for our use
>> cases in the template interpreter. In fact, we only need to do a single FENCE R,RW after a normal memory
>> load in order to implement a load-acquire operation. We should remove those unnecessary fences for both
>> performance reasons and for consistency with the rest of the port (i.e., C1 and C2 JIT).
>> 
>> Testing:
>> - [x] JCstress
>> - [x] hs-tier1 - hs-tier4
>> - [x] ~5% improvement on SPECJbb2005 score (-Xint -XX:+UseParallelGC)
>
> Thank you!

Thanks! @robehn @RealFYang

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PR Comment: https://git.openjdk.org/jdk/pull/21248#issuecomment-2387996811