RFR: 8329035: New Data Destination instructions support [v2]
Steve Dohrmann
sdohrmann at openjdk.org
Fri Sep 6 21:44:49 UTC 2024
On Wed, 4 Sep 2024 22:05:03 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:
>> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
>>
>> function name changes based on review comments
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 1361:
>
>> 1359: InstructionMark im(this);
>> 1360: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1361: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> The input_size_in_bits could be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1403:
>
>> 1401: InstructionMark im(this);
>> 1402: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1403: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> The input_size_in_bits could be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1461:
>
>> 1459:
>> 1460: void Assembler::eaddb(Register dst, Address src1, Register src2, bool no_flags) {
>> 1461: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>
> InstructionMark im(this) is missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1475:
>
>> 1473: void Assembler::eaddb(Register dst, Register src, int imm8, bool no_flags) {
>> 1474: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1475: // (void) evex_prefix_and_encode_ndd(src->encoding(), dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes);
>
> Looks like the commented line is left over.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1780:
>
>> 1778: void Assembler::eandw(Register dst, Register src1, Register src2, bool no_flags) {
>> 1779: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1780: (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>
> This should be VEX_SIMD_66 instead of VEX_SIMD_NONE.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1793:
>
>> 1791: InstructionMark im(this);
>> 1792: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1793: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit here.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1819:
>
>> 1817: InstructionMark im(this);
>> 1818: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1819: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1835:
>
>> 1833: InstructionMark im(this);
>> 1834: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 1835: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 1837:
>
>> 1835: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>> 1836: evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>> 1837: emit_operand(src1, src2, 0);
>
> emit_int8(0x23) is missing before call to emit_operand().
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 2642:
>
>> 2640:
>> 2641: void Assembler::edecl(Register dst, Address src, bool no_flags) {
>> 2642: // Don't use it directly. Use MacroAssembler::decrement() instead.
>
> This comment could be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 2721:
>
>> 2719: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 2720: int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>> 2721: emit_int16((unsigned char)0xA7, (0xE8 | encode));
>
> Should this be 0xF7?
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 4583:
>
>> 4581: InstructionMark im(this);
>> 4582: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 4583: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 4637:
>
>> 4635: InstructionMark im(this);
>> 4636: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 4637: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6593:
>
>> 6591:
>> 6592: void Assembler::erolq(Register dst, Register src, bool no_flags) {
>> 6593: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>
> vex_w should be true here.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6647:
>
>> 6645: assert(isShiftCount(imm8), "illegal shift count");
>> 6646: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6647: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6670:
>
>> 6668: InstructionMark im(this);
>> 6669: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6670: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6686:
>
>> 6684: }
>> 6685:
>> 6686: void Assembler::esall(Register dst, Register src, int imm8, bool no_flags) {
>
> assert(isShiftCount(imm8), "illegal shift count") missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6694:
>
>> 6692: emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
>> 6693: }
>> 6694: }
>
> Should this be (0xE0 | encode)?
Yes, thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6722:
>
>> 6720: }
>> 6721:
>> 6722: void Assembler::esarl(Register dst, Address src, int imm8, bool no_flags) {
>
> assert(isShiftCount(imm8), "illegal shift count") missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6725:
>
>> 6723: InstructionMark im(this);
>> 6724: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6725: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6748:
>
>> 6746: InstructionMark im(this);
>> 6747: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6748: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6764:
>
>> 6762: }
>> 6763:
>> 6764: void Assembler::esarl(Register dst, Register src, int imm8, bool no_flags) {
>
> assert(isShiftCount(imm8), "illegal shift count") missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6794:
>
>> 6792: InstructionMark im(this);
>> 6793: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6794: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 6819:
>
>> 6817: void Assembler::esbbl(Register dst, Register src1, Address src2) {
>> 6818: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 6819: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 7546:
>
>> 7544: InstructionMark im(this);
>> 7545: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 7546: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 7572:
>
>> 7570: InstructionMark im(this);
>> 7571: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 7572: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bits should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 7600:
>
>> 7598: InstructionMark im(this);
>> 7599: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 7600: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>
> input_size_in_bytes should be EVEX_32bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 7645:
>
>> 7643: void Assembler::exorw(Register dst, Register src1, Register src2, bool no_flags) {
>> 7644: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 7645: (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>
> VEX_SIMD_NONE should be VEX_SIMD_66.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 7662:
>
>> 7660: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 7661: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
>> 7662: evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>
> input_size_in_bits could be EVEX_16bit.
> VEX_SIMD_NONE should be VEX_SIMD_66.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 12251:
>
>> 12249:
>> 12250: void Assembler::edecl(Register dst, Register src, bool no_flags) {
>> 12251: // Don't use it directly. Use MacroAssembler::deccrementl() instead.
>
> This comment can be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 12751:
>
>> 12749: }
>> 12750: if (nds_is_ndd) attributes->set_extended_context();
>> 12751: bool is_extended = adr.base_needs_rex2() || adr.index_needs_rex2() || nds_enc >= 16 || xreg_enc >= 16 || nds_is_ndd || force_evex;
>
> If is_evex_instruction() is set for ndd and nf already at calling place as in my previous review comments, then is_extended could remain as before:
> bool is_extended = adr.base_needs_rex2() || adr.index_needs_rex2() || nds_enc >= 16 || xreg_enc >= 16;
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 12841:
>
>> 12839:
>> 12840: clear_managed();
>> 12841: if ((UseAVX > 2 && !attributes->is_legacy_mode()) || nds_is_ndd || force_evex)
>
> If is_evex_instruction() is set for ndd and nf already at calling place as in my previous review comments, then this if could remain as before: if (UseAVX > 2 && !attributes->is_legacy_mode())
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 13706:
>
>> 13704:
>> 13705: void Assembler::eincl(Register dst, Register src, bool no_flags) {
>> 13706: // Don't use it directly. Use MacroAssembler::incrementl() instead.
>
> This comment could be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 14788:
>
>> 14786: void Assembler::edecl(Register dst, Register src, bool no_flags) {
>> 14787: // Don't use it directly. Use MacroAssembler::decrementl() instead.
>> 14788: // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
>
> This comment could be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 14803:
>
>> 14801: void Assembler::edecq(Register dst, Register src, bool no_flags) {
>> 14802: // Don't use it directly. Use MacroAssembler::incrementq() instead.
>> 14803: // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
>
> This comment could be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 14817:
>
>> 14815:
>> 14816: void Assembler::edecq(Register dst, Address src, bool no_flags) {
>> 14817: // Don't use it directly. Use MacroAssembler::increment() instead.
>
> This comment could be removed.
Done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 14883:
>
>> 14881: void Assembler::eimulq(Register dst, Register src, bool no_flags) {
>> 14882: InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 14883: int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, no_flags);
>
> Is there a reason we are not calling the evex_prefix_and_encode_nf here?
No reason. Thanks, fixed.
> src/hotspot/cpu/x86/assembler_x86.cpp line 14900:
>
>> 14898: void Assembler::eimulq(Register src, bool no_flags) {
>> 14899: InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 14900: int encode = vex_prefix_and_encode(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, no_flags);
>
> Is there a reason we are not calling the evex_prefix_and_encode_nf here?
No reason. Thanks, fixed.
> src/hotspot/cpu/x86/assembler_x86.cpp line 15827:
>
>> 15825:
>> 15826: void Assembler::esarq(Register dst, Address src, int imm8, bool no_flags) {
>> 15827: InstructionMark im(this);
>
> assert(isShiftCount(imm8 >> 1), "illegal shift count") is missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 15885:
>
>> 15883: InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 15884: int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
>> 15885: emit_int16((unsigned char)0xD1, (0xF8 | encode));
>
> This should be:
> emit_int16((unsigned char)0xD3, (0xF8 | encode));
> Shift by cl and not shift by 1.
Thanks, fixed.
> src/hotspot/cpu/x86/assembler_x86.cpp line 15920:
>
>> 15918: }
>> 15919:
>> 15920: void Assembler::esbbq(Register dst, Register src1, Address src2) {
>
> InstructionMark im(this) is missing.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.cpp line 15934:
>
>> 15932:
>> 15933: void Assembler::esbbq(Register dst, Register src1, Register src2) {
>> 15934: InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>
> vex_w should be true here?
Yes, thanks, fixed.
> src/hotspot/cpu/x86/assembler_x86.cpp line 16039:
>
>> 16037: assert(isShiftCount(imm8 >> 1), "illegal shift count");
>> 16038: InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
>> 16039: attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
>
> input_size_in_bits should be EVEX_64bit.
Thanks, done.
> src/hotspot/cpu/x86/assembler_x86.hpp line 796:
>
>> 794: void evex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false) {
>> 795: vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ true , /* force_evex */ true, no_flags);
>> 796: }
>
> The additional parameter force_evex could be removed and the above could be encoded as:
> attributes.set_is_evex_instruction();
> vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ true , no_flags);
Done.
> src/hotspot/cpu/x86/assembler_x86.hpp line 800:
>
>> 798: void evex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false) {
>> 799: vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ false , /* force_evex */ true, no_flags);
>> 800: }
>
> The additional parameter force_evex could be removed and the above could be encoded as:
> attributes.set_is_evex_instruction();
> vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ false, no_flags);
Done.
> src/hotspot/cpu/x86/assembler_x86.hpp line 811:
>
>> 809: int evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
>> 810: InstructionAttr *attributes, bool no_flags = false) {
>> 811: return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true , /* force_evex */ true, no_flags);
>
> The additional parameter force_evex could be removed and the above could be encoded as:
> attributes.set_is_evex_instruction();
> return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags);
Done.
> src/hotspot/cpu/x86/assembler_x86.hpp line 816:
>
>> 814: int evex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
>> 815: InstructionAttr *attributes, bool no_flags = false) {
>> 816: return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, /* force_evex */ true, no_flags);
>
> The additional parameter force_evex could be removed and the above could be encoded as:
> attributes.set_is_evex_instruction();
> return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, no_flags);
Done.
-------------
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745368
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745414
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745855
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745464
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745537
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745586
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745637
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745667
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745720
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745763
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745805
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745902
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745952
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746057
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746110
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746146
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PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746523
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746279
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746371
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746421
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746584
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746627
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746668
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746694
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746761
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746864
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746917
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747746991
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747103
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745258
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745324
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747151
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747206
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747253
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747294
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747371
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747439
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747500
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747532
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747588
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747614
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747747648
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747744994
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745103
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745148
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1747745195
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