RFR: 8339790: Support Intel APX setzucc instruction [v3]

[Jatin Bhateja]

> - Support APX variant of SETcc, which supports zero-upper semantics (full register writer). Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The
> condition code suffix (cc) indicates the condition being tested for. Additionally, if ND = 1 and the destination is a GPR, then also set the upper 56 bits of the GPR to 0.
> - This saves emitting an explicit MOVZX instruction after setCC.
> - These new instructions are encoded using 4 byte Extended EVEX encoding.
> 
> Validation performed over stand alone test point using Intel SDE.
> 
> Best Regards,
> Jatin

Jatin Bhateja has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains four commits:

 - Review comments resolution.
 - Merge branch 'master' of http://github.com/openjdk/jdk into JDK-8339790
 - Review resolutions.
 - 8339790: Support Intel APX setzucc instruction.

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Changes: https://git.openjdk.org/jdk/pull/20920/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=20920&range=02
  Stats: 77 lines in 7 files changed: 26 ins; 25 del; 26 mod
  Patch: https://git.openjdk.org/jdk/pull/20920.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/20920/head:pull/20920

PR: https://git.openjdk.org/jdk/pull/20920