RFR: 8339790: Support Intel APX setzucc instruction [v6]

[Jatin Bhateja]

> - Support APX variant of SETcc, which supports zero-upper semantics (full register writer). Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The
> condition code suffix (cc) indicates the condition being tested for. Additionally, if ND = 1 and the destination is a GPR, then also set the upper 56 bits of the GPR to 0.
> - This saves emitting an explicit MOVZX instruction after setCC.
> - These new instructions are encoded using 4 byte Extended EVEX encoding.
> 
> Validation performed over stand alone test point using Intel SDE.
> 
> Best Regards,
> Jatin

Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:

  Post NDD patch cleanups

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/20920/files
  - new: https://git.openjdk.org/jdk/pull/20920/files/dc37dea6..8673c736

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=20920&range=05
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=20920&range=04-05

  Stats: 6 lines in 1 file changed: 0 ins; 5 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/20920.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/20920/head:pull/20920

PR: https://git.openjdk.org/jdk/pull/20920