Integrated: 8339790: Support Intel APX setzucc instruction

[Jatin Bhateja]

On Mon, 9 Sep 2024 19:36:51 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> - Support APX variant of SETcc, which supports zero-upper semantics (full register writer). Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The
> condition code suffix (cc) indicates the condition being tested for. Additionally, if ND = 1 and the destination is a GPR, then also set the upper 56 bits of the GPR to 0.
> - This saves emitting an explicit MOVZX instruction after setCC.
> - These new instructions are encoded using 4 byte Extended EVEX encoding.
> 
> Validation performed over stand alone test point using Intel SDE.
> 
> Best Regards,
> Jatin

This pull request has now been integrated.

Changeset: 90e92f98
Author:    Jatin Bhateja <jbhateja at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/90e92f98a6685b196b979853436668cf2b9f2117
Stats:     73 lines in 7 files changed: 22 ins; 25 del; 26 mod

8339790: Support Intel APX setzucc instruction

Reviewed-by: sviswanathan, jkarthikeyan, kvn

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PR: https://git.openjdk.org/jdk/pull/20920