RFR: 8340590: RISC-V: C2: Small improvement to vector gather load and scattter store

[Dingli Zhang]

On Mon, 23 Sep 2024 05:48:29 GMT, Fei Yang <fyang at openjdk.org> wrote:

> PS: Seems to me that this could be further improved after some more thinking. These `vmv_v_v` instructions could be eliminated if we use `idx` directly as input for `vsll_vi`, like this addon change:
> 
> ```
> diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad
> index a3c426e71d2..510c0ff5d46 100644
> --- a/src/hotspot/cpu/riscv/riscv_v.ad
> +++ b/src/hotspot/cpu/riscv/riscv_v.ad
> @@ -4898,8 +4898,7 @@ instruct gather_loadS(vReg dst, indirect mem, vReg idx) %{
>      BasicType bt = Matcher::vector_element_basic_type(this);
>      Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
>      __ vsetvli_helper(bt, Matcher::vector_length(this));
> -    __ vmv_v_v(as_VectorRegister($dst$$reg), as_VectorRegister($idx$$reg));
> -    __ vsll_vi(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), (int)sew);
> +    __ vsll_vi(as_VectorRegister($dst$$reg), as_VectorRegister($idx$$reg), (int)sew);
>      __ vluxei32_v(as_VectorRegister($dst$$reg), as_Register($mem$$base),
>                    as_VectorRegister($dst$$reg));
>   %}
> @@ -4932,8 +4931,7 @@ instruct gather_loadS_masked(vReg dst, indirect mem, vReg idx, vRegMask_V0 v0, v
>      BasicType bt = Matcher::vector_element_basic_type(this);
>      Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
>      __ vsetvli_helper(bt, Matcher::vector_length(this));
> -    __ vmv_v_v(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg));
> -    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg), (int)sew);
> +    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg), (int)sew);
>      __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg),
>                 as_VectorRegister($dst$$reg));
>      __ vluxei32_v(as_VectorRegister($dst$$reg), as_Register($mem$$base),
> @@ -4972,8 +4970,7 @@ instruct scatter_storeS(indirect mem, vReg src, vReg idx, vReg tmp) %{
>      BasicType bt = Matcher::vector_element_basic_type(this, $src);
>      Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
>      __ vsetvli_helper(bt, Matcher::vector_length(this, $src));
> -    __ vmv_v_v(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg));
> -    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg), (int)sew);
> +    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg), (int)sew);
>      __ vsuxei32_v(as_VectorRegister($src$$reg), as_Register($mem$$base),
>                    as_VectorRegister($tmp$$reg));
>    %}
> @@ -5006,8 +5003,7 @@ instruct scatter_storeS_masked(indirect mem, vReg src, vReg idx, vRegMask_V0 v0,
>      BasicType bt = Matcher::vector_element_basic_type(this, $src);
>      Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
>      __ vsetvli_helper(bt, Matcher::vector_length(this, $src));
> -    __ vmv_v_v(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg));
> -    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg), (int)sew);
> +    __ vsll_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($idx$$reg), (int)sew);
>      __ vsuxei32_v(as_VectorRegister($src$$reg), as_Register($mem$$base),
>                    as_VectorRegister($tmp$$reg), Assembler::v0_t);
> ```

It looks good, thanks for all.

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PR Comment: https://git.openjdk.org/jdk/pull/21123#issuecomment-2367314486