RFR: 8334060: Implementation of Late Barrier Expansion for G1 [v24]

[Fei Yang]

On Wed, 25 Sep 2024 04:22:49 GMT, Roberto Castañeda Lozano <rcastanedalo at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.ad line 257:
>> 
>>> 255:                       RegSet::of($res$$Register) /* no_preserve */);
>>> 256:     __ mov($tmp1$$Register, $oldval$$Register);
>>> 257:     __ mov($tmp2$$Register, $newval$$Register);
>> 
>> Hi, I don't quite understand these two register-register moves here. Seems to me that we could pass `oldval` and `newval` to `cmpxchg` directly as `cmpxchg` won't modify them, which help us save these two moves. Did I miss anything? Thanks.
>
> Hi Fei, good catch, thanks. These moves have been around since the changes were initially prototyped, and are indeed unnecessary. Note that micro-optimization of the barrier code for atomic memory accesses has not been a focus of this JEP since we have not found any performance reason to do it at the macro level. Having said that, the moves are just wasteful and (perhaps more importantly) make the code harder to read and maintain, so I just removed them (commit 2c7f374e).

Thanks for the update. It now looks cleaner and easier to understand. BTW: Seems that RISC-V part bears a similar issue. I will discuss with @feilongjiang and hopefully we will come up with a similar fix.

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PR Review Comment: https://git.openjdk.org/jdk/pull/19746#discussion_r1774695093