RFR: 8341146: RISC-V: Unnecessary fences used for load-acquire in template interpreter

[Feilong Jiang]

Hi, please consider.

RISC-V does not currently have plain load and store opcodes with aq or rl annotations, load-acquire and
store-release operations are implemented using fences instead. Initially, we followed the RISC-V spec
and placed FENCE RW,RW fence in front of load-acquire operation when porting the template interpreter.
The purpose is to enforce a store-release-to-load-acquire ordering (where there must be a FENCE RW,RW
between the store-release and load-acquire). But it turns out these fences are unnecessary for our use
cases in the template interpreter. In fact, we only need to do a single FENCE R,RW after a normal memory
load in order to implement a load-acquire operation. We should remove those unnecessary fences for both
performance reasons and for consistency with the rest of the port (i.e., C1 and C2 JIT).

Testing:
- [x] JCstress
- [x] hs-tier1 - hs-tier4
- [x] ~5% improvement on SPECJbb2005 score (-Xint -XX:+UseParallelGC)

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Commit messages:
 - remove unnecessary membar in template interpreter

Changes: https://git.openjdk.org/jdk/pull/21248/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=21248&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8341146
  Stats: 9 lines in 1 file changed: 0 ins; 9 del; 0 mod
  Patch: https://git.openjdk.org/jdk/pull/21248.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/21248/head:pull/21248

PR: https://git.openjdk.org/jdk/pull/21248