RFR: 8334060: Implementation of Late Barrier Expansion for G1 [v23]
Roberto Castañeda Lozano
rcastanedalo at openjdk.org
Mon Sep 30 07:59:45 UTC 2024
On Wed, 18 Sep 2024 07:57:15 GMT, Roberto Castañeda Lozano <rcastanedalo at openjdk.org> wrote:
>> Roberto Castañeda Lozano has updated the pull request incrementally with seven additional commits since the last revision:
>>
>> - Assert that unneeded stub tmp registers are not initialized in x64 and aarch64 platforms
>> - Set tmp registers to noreg by default in G1PreBarrierStubC2::initialize_registers, for consistency
>> - Merge remote-tracking branch 'snazarkin/arm32-JDK-8334060-g1-late-barrier-expansion' into JDK-8334060-g1-late-barrier-expansion
>> - Restore some asserts
>> - Default values for tmp regs of G1PostBarrierStubC2
>> - 8334060: [arm32] Implementation of Late Barrier Expansion for G1
>> - 8330685: [arm32] share barrier spilling logic
>
> Thanks for the arm 32-bits port @snazarkin! Merged in commit 3957c03f.
> Besides the arm 32-bits port, @snazarkin's changeset includes adding the possibility to use a third temporary register in the platform-independent class `G1PostBarrierStubC2`. This temporary register (`G1PostBarrierStubC2::_tmp3`) is initialized to `noreg` by default in `G1PostBarrierStubC2::initialize_registers`, so no other platform should be affected.
> Hi @robcasloz, riscv port cleanup is available at [feilongjiang at 1297f60](https://github.com/feilongjiang/jdk/commit/1297f6086e1de62196e2acddf2f7c86a29619dd7), would you please help to apply it?
Done (commit 14483b83), thanks!
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PR Comment: https://git.openjdk.org/jdk/pull/19746#issuecomment-2382377364
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