RFR: 8353665: RISC-V: IR verification fails in TestSubNodeFloatDoubleNegation.java

[Manuel Hässig]

On Thu, 3 Apr 2025 16:57:19 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review this patch?
> The newly added TestSubNodeFloatDoubleNegation.java (in https://github.com/openjdk/jdk/pull/24150) is to check `0 - (0 - x)` is not folded to `x` for float and double.
> I have manually checked the IR and generated assembly code, it's not folded on riscv either, just there is an extra SubF in some code path.
> So, the fix for this test on riscv should be simply make the check as `>= 2` rather than `2`.
> 
> Tested on both x86 and riscv64.
> 
> Thanks

test/hotspot/jtreg/compiler/floatingpoint/TestSubNodeFloatDoubleNegation.java line 59:

> 57:     // performed as float operations.
> 58:     @IR(counts = { IRNode.SUB, "2" }, applyIfPlatform = {"riscv64", "false"})
> 59:     @IR(counts = { IRNode.SUB, ">= 2" }, applyIfPlatform = {"riscv64", "true"})

Would it perhaps make sense to fix the number of `SubNode`s or does the `Float16` code add a bunch of them on RISC-V?

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PR Review Comment: https://git.openjdk.org/jdk/pull/24421#discussion_r2028346592