RFR: 8353665: RISC-V: IR verification fails in TestSubNodeFloatDoubleNegation.java

[Manuel Hässig]

On Thu, 3 Apr 2025 16:57:19 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review this patch?
> The newly added TestSubNodeFloatDoubleNegation.java (in https://github.com/openjdk/jdk/pull/24150) is to check `0 - (0 - x)` is not folded to `x` for float and double.
> I have manually checked the IR and generated assembly code, it's not folded on riscv either, just there is an extra SubF in some code path.
> So, the fix for this test on riscv should be simply make the check as `>= 2` rather than `2`.
> 
> Tested on both x86 and riscv64.
> 
> Thanks

To me `B5`kind of looks like a backup codepath (see branch at 042). But I cannot see what `R7`is there.

One option I see would be to match two `SUB_HF` nodes for RISC-V, since it seems to always generate two of those. The only reason I match on `SUB` in the half float case is that I also do not have `supports_avx512_fp16`. I think I will file an RFE for that separately.

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PR Comment: https://git.openjdk.org/jdk/pull/24421#issuecomment-2778113274