RFR: 8352675: Support Intel AVX10 converged vector ISA feature detection [v4]

[Vladimir Ivanov]

On Wed, 23 Apr 2025 05:47:21 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> - Intel AVX10[1] extends and enhances the capabilities of Intel AVX-512 to benefit all Intel® products and will be the vector ISA of choice moving into the future. 
>> - It supports a new ISA versioning scheme which simplifies the existing AVX512 feature enumeration scheme. Feature set supported by an AVX10 ISA version will be supported by all the versions above it.
>> - The initial, fully-featured version of Intel® AVX10 will be enumerated as Version 2 (denoted as Intel® AVX10.2). This will include the new ISA extension over the existing AVX512 instructions. 
>> - An early version of Intel® AVX10 (Version 1, or Intel® AVX10.1) that only enumerates the Intel® AVX-512 instruction set at 128, 256, and 512 bits will be enabled on the Granite Rapids Server for software pre-enabling.
>> 
>> This patch adds the necessary CPUID feature detection for AVX10 ISA version 1 and 2.  In terms of architectural state save restoration, AVX10 is isomorphic to AVX512 support up till Granite Rapids. State components affected by AVX10 extension include SSE, AVX, Opmask, ZMM_Hi256, and Hi16_ZMM registers. 
>> 
>> The patch has been regressed through tier1 and jvmci tests 
>> 
>> Please review and share your feedback.
>> 
>> Best Regards,
>> Jatin
>> 
>> [1] https://www.intel.com/content/www/us/en/content-details/844829/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html
>
> Jatin Bhateja has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains four additional commits since the last revision:
> 
>  - Add dynamic sized feature vectors
>  - Merge branch 'master' of http://github.com/openjdk/jdk into JDK-8352675
>  - dropping unneeded feature enabling/checks
>  - 8352675: Support Intel AVX10 converged vector ISA feature detection

It looks much better! Thanks, Jatin.

I'm curious why don't you represent feature bitmap as a POD (with all the accessors on it) and pass it around by value when needed? (It's size will vary across platforms, but will be fixed at runtime.) It should significantly simplify the implementation. 

As an example, take a look at `RegMask` in C2. It accommodates significantly more bits than needed for `VM_Version`.

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PR Review: https://git.openjdk.org/jdk/pull/24329#pullrequestreview-2789109933