RFR: 8355074: RISC-V: C2: Support Vector-Scalar version of Zvbb Vector And-Not instruction [v2]

[Feilong Jiang]

On Thu, 24 Apr 2025 12:49:17 GMT, Anjian-Wen <duke at openjdk.org> wrote:

>> support zvbb vand-not vector-scalar version, which Op1 is the sign-extended or truncated value in scalar register rs1
>> add C2 match rule
>> add related Tests in IRNode structure
>> 
>> passed jtreg test test/hotspot/jtreg/compiler/vectorapi/*
>
> Anjian-Wen has updated the pull request incrementally with one additional commit since the last revision:
> 
>   add prefix for test String

Thanks! Overall looks good, with one minor suggestion.

src/hotspot/cpu/riscv/riscv_v.ad line 416:

> 414: // vector-immediate add (unpredicated)
> 415: 
> 416: instruct vaddI_vi(vReg dst, vReg src1, immI5 con) %{

Perhaps we can do these naming refactorings in a separate PR first. This will look cleaner.

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Marked as reviewed by fjiang (Committer).

PR Review: https://git.openjdk.org/jdk/pull/24709#pullrequestreview-2791413687
PR Review Comment: https://git.openjdk.org/jdk/pull/24709#discussion_r2058574940