RFR: 8322174: RISC-V: C2 VectorizedHashCode RVV Version [v10]

[Yuri Gaevsky]

On Mon, 4 Aug 2025 08:43:06 GMT, Yuri Gaevsky <duke at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2062:
>> 
>>> 2060:   vmv_s_x(v_powmax, pow31_highest);
>>> 2061: 
>>> 2062:   vsetvli(consumed, cnt, Assembler::e32, Assembler::m4);
>> 
>> What's the performance look like with a smaller `lmul` (m1 or m2)? I am asking this because there are hardwares there (like SG2044) with a VLEN of 128 instead of 256 like on K1.
>
>> What's the performance look like with a smaller `lmul` (m1 or m2)? I am asking this because there are hardwares there (like SG2044) with a VLEN of 128 instead of 256 like on K1.
> 
> Sure, I'll do it, thanks for the suggestion.

Please see it [here](https://github.com/openjdk/jdk/pull/17413#issuecomment-3150754134).

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PR Review Comment: https://git.openjdk.org/jdk/pull/17413#discussion_r2251529819