RFR: 8343689: AArch64: Optimize MulReduction implementation [v8]

[Mikhail Ablakatov]

On Fri, 11 Jul 2025 08:40:40 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 4073:
>> 
>>> 4071:     f(0b101111, 15, 10), rf(Zn, 5), rf(Zd, 0);
>>> 4072:   }
>>> 4073: 
>> 
>> This pattern should be in a section _SVE Integer Reduction_, C4.1.37. I'm not sure if any other instructions in that group are defined yet, but if not please start the section.
>
> Sorry, the unpredicated version should be in the _SVE Integer Misc - Unpredicated_ section.

Are you asking to move it to another existing section in the file or create a new one? If it's the former, could you point me to the section in the file - I can see neither `sve_ftssel` nor `sve_fexpa` defined. If the latter, in Arm ARM *C4.1.41 SVE Integer Misc - Unpredicated* is followed by *C4.1.42 SVE Element Count*, so the patch places `sve_movprfx` definition right before `sve_cnt*`; I also don't see an opportunity to define an `INSN` for this section as encodings of the instructions within the section do not follow a single pattern.

If it's something else completely, please elaborate.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23181#discussion_r2263251283