RFR: 8343689: AArch64: Optimize MulReduction implementation [v8]

[Mikhail Ablakatov]

On Sat, 9 Aug 2025 07:29:26 GMT, Andrew Haley <aph at openjdk.org> wrote:

> Please try to organize things the same way as the Decode section of the ARM.

Do you refer to *C4: A64 Instruction Set Encoding*?

> Insert a new section called SVE Integer Misc - Unpredicated after SVE bitwise shift by immediate (predicated) and put this pattern there.

I assume you might have misinterpreted  **predicated** SVE bitwise shift for **unpredicated**. 

In the *C4: A64 Instruction Set Encoding*, *C4.1.41 SVE Integer Misc - Unpredicated* follows *C4.1.40 SVE Bitwise Shift - Unpredicated* which is not implemented by `src/hotspot/cpu/aarch64/assembler_aarch64.hpp` as far as I can tell. Suggested *SVE bitwise shift by immediate (predicated)* falls into *C4.1.34 SVE Bitwise Shift - Predicated*.  If this change is to follow the ordering in *C4: A64 Instruction Set Encoding*, the next proceeding implemented instruction class for `sve_movprfx` (from *C4.1.41*) should be [SVE stack frame adjustment](https://github.com/openjdk/jdk/pull/23181/files/4593a5d717024df01769625993c2b769d8dde311#diff-203c5bbfa5307b5cc529c80acf90e764260db018ed658b949421f91190c56982L3686) which falls into *C4.1.38 SVE Stack Allocation*. The next following implemented instruction class should be [SVE element count](https://github.com/openjdk/jdk/pull/23181/files/4593a5d717024df01769625993c2b769d8dde311#diff-203c5bbfa5307b5cc529c80acf90e764260db018ed658b949421f91190c5698
 2L4067) (inconveniently named something else in the source file) which falls into *C4.1.42 SVE Element Count*. The two instruction classes doesn't follow each other in the file, unfortunately, so it's one or the other. Currently it's the latter.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23181#discussion_r2272750216