RFR: 8361582: AArch64: Some ConH values cannot be replicated with SVE [v4]

[Bhavana Kilambi]

On Wed, 13 Aug 2025 13:01:57 GMT, Andrew Haley <aph at openjdk.org> wrote:

> > The destination register is an FPR. If we would want to modify this to generate a move to a scratch register instead (something similar to loadConI) then we would have to change the destination register to `iregI`
> 
> This is the part I don't understand. Why would you have to change the destination register to `iregI`? I wouldn't.
> 
> ```
> instruct loadConH(vRegF dst, immH con) %{
>   match(Set dst con);
>   format %{
>     "something"
>   %}
>   ins_encode %{
>     __ movw(rscratch1, $con$$constant);
>     __ fmovs($dst$$reg, rscratch1);
>   %}
> ```

Thanks. Yes I could do that (as I mentioned earlier in my comment), but I was trying to avoid the extra mov -`fmov`. Just that I wasn't sure if this version would be faster than an `ldr`. But it just occured to me that I could compare the latencies. `ldr` on V1 has a latency of 4 cyc and `mov` + `fmov` is 1 + 2 = 3 cyc. So it probably makes sense to go with two moves. Thanks!

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PR Comment: https://git.openjdk.org/jdk/pull/26589#issuecomment-3184163893