RFR: 8322174: RISC-V: C2 VectorizedHashCode RVV Version [v25]

[Yuri Gaevsky]

On Thu, 14 Aug 2025 06:45:39 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Yuri Gaevsky has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   - addressed reviewer's comments/suggestions.
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1920:
> 
>> 1918:                                         BasicType eltype)
>> 1919: {
>> 1920:   assert(!UseRVV, "sanity");
> 
> Although not dierectly related, can you fix indentation issue of switch-case in this function, `C2_MacroAssembler::arrays_hashcode_elsize` and `C2_MacroAssembler::arrays_hashcode_elload`?
> We need add two spaces on the left of each case.

Sure.

> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2111:
> 
>> 2109:                                                  Register src,
>> 2110:                                                  BasicType eltype) {
>> 2111:   assert((T_INT == eltype) || (vdst != vtmp), "should be");
> 
> Or simply: `assert_different_registers(vdst, vtmp).` ?

Nice catch, done

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/17413#discussion_r2277442246
PR Review Comment: https://git.openjdk.org/jdk/pull/17413#discussion_r2277442681