RFR: 8361582: AArch64: Some ConH values cannot be replicated with SVE [v6]

[Andrew Haley]

On Fri, 15 Aug 2025 08:48:56 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64.ad line 7100:
>> 
>>> 7098:     } else {
>>> 7099:       __ movw(rscratch1, imm);
>>> 7100:     }
>> 
>> Is this a Neoverse-specific optimization? On Apple M1, `mov x0, #0` is handled by renaming (so never issues) but `mov x0, xzr` is not eliminated. Let's go for the simplest here, this is too fussy.
>> 
>> Suggestion:
>> 
>>     __ movw(rscratch1, (uint32_t)$con$$constant);
>
> Thanks for letting me know about the optimization on Apple. After consulting the Software optimization guide, it looks like a `mov w, #0` is also a zero cycle move along with the `movw w, zr` instruction on V1/N2/V2 and is a normal ALU op on N1. Makes sense to eliminate the instruction. I will make the changes you suggested in next PS.

Thanks. I know from personal experience that it's hard to resist every tiny optimization, but some things aren't worth it.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26589#discussion_r2278706946