RFR: 8365732: RISC-V: implement AES CTR intrinsics

[Anjian Wen]

On Tue, 15 Jul 2025 09:13:16 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Hi everyone, please help review this patch which Implement the _counterMode_AESCrypt with Zvkned. On my QEMU, with Zvkned extension enabled, the tests in test/hotspot/jtreg/compiler/codegen/aes/ Passed.
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2745:
> 
>> 2743:     __ vsetivli(x0, 4, Assembler::e32, Assembler::m1);
>> 2744:     __ vrev8_v(v31, v31, Assembler::VectorMask::v0_t); // convert big-endien to little-endian
>> 2745:     __ vadd_vi(v31, v31, 1, Assembler::VectorMask::v0_t);
> 
> Are you sure this is correct? See `com.sun.crypto.provider.CounterMode::increment`.

Thanks for the review. I'm still developing it.
Regarding the growth of the counter array, it should use 8 bytes to store the count.  I use 4 Byte here according to OpenSSL aes-ctr code, I will try to fix it later
https://github.com/openssl/openssl/blob/master/crypto/aes/asm/aes-riscv64-zvkb-zvkned.pl#L242

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2230736352