RFR: 8364305: Support AVX10 saturating floating point conversion instructions

[Jatin Bhateja]

On Mon, 25 Aug 2025 05:20:23 GMT, Mohamed Issa <missa at openjdk.org> wrote:

> Intel® AVX10 ISA [1] extensions added new saturating floating point conversion instructions which comply with definitions in section 5.8 of the 2019 IEEE-754 standard. They can compute floating point to integral type conversions while also handling special inputs such as NaN, +Infinity, and -Infinity.
> 
> Without AVX10.2, the current approach starts by converting the floating point value(s) in the source register to the desired integral value(s) in the destination register. In the scalar case, the CVTTSS2SI (single precision) or CVTTSD2SI (double precision) instruction is used. In the vector case, the CVTTPS2DQ (single precision) or CVTTPD2DQ (double precision) is used. However, if the source contains a special value (NaN, -Infinity, +Infinity, <= Integer.MIN_VALUE, or >= Integer.MAX_VALUE), extra handling is required. The specific sequence of instructions involved depends on the source (single precision vs double precision), destination (long, integer, short, or byte), level of parallelization (scalar vs vector), and supported AVX extension type. Essentially though, the special values are mapped to values (NaN -> 0, -Infinity, <= Integer.MIN_VALUE -> Integer.MIN_VALUE, +Infinity, >= Integer.MAX_VALUE -> Integer.MAX_VALUE) in the integer range with the help of a few temporary regist
 ers to store intermediate results.
> 
> This change uses the new AVX10.2 scalar (VCVTTSS2SIS or  VCVTTSD2SIS) and vector (VCVTTPS2QQS, VCVTTPS2DQS, VCVTTPD2QQS, and VCVTTPD2DQS) instructions on supported platforms to avoid the extra handling described above. Also, the JTREG tests listed below were used to verify correctness with `-XX:-UseSuperWord` / `-XX:+UseSuperWord` options to exercise both scalar and vector paths. The baseline build used is [OpenJDK v26-b11](https://github.com/openjdk/jdk/releases/tag/jdk-26%2B11).
> 
> 1. `jtreg:test/hotspot/jtreg/compiler/codegen/TestByteDoubleVect.java`
> 2. `jtreg:test/hotspot/jtreg/compiler/codegen/TestByteFloatVect.java`
> 3. `jtreg:test/hotspot/jtreg/compiler/codegen/TestIntDoubleVect.java`
> 4. `jtreg:test/hotspot/jtreg/compiler/codegen/TestIntFloatVect.java`
> 5. `jtreg:test/hotspot/jtreg/compiler/codegen/TestLongDoubleVect.java`
> 6. `jtreg:test/hotspot/jtreg/compiler/codegen/TestLongFloatVect.java`
> 7. `jtreg:test/hotspot/jtreg/compiler/codegen/TestShortDoubleVect.java`
> 8. `jtreg:test/hotspot/jtreg/compiler/codegen/TestShortFloatVect.java`
> 
> [1] https://www.intel.com/content/www/us/en/content-details/856721/intel-advanced-vector-extensions-10-2-int...

src/hotspot/cpu/x86/assembler_x86.cpp line 2406:

> 2404: }
> 2405: 
> 2406: void Assembler::evcvttpd2qqs(XMMRegister dst, XMMRegister src, int vector_len) {

Please also add memory operand flavour of these assembler routines.

src/hotspot/cpu/x86/x86.ad line 7776:

> 7774: %}
> 7775: 
> 7776: instruct cast2DtoX_reg_evex(vec dst, vec src, rFlagsReg cr) %{

Vector instruction do not effect EFLAGS register.

src/hotspot/cpu/x86/x86.ad line 7776:

> 7774: %}
> 7775: 
> 7776: instruct cast2DtoX_reg_evex(vec dst, vec src, rFlagsReg cr) %{

How about adding a CICS flavour of these patterns. As now we have a single instruction to cover entire conversion semantics memory operand patterns will be useful.

src/hotspot/cpu/x86/x86.ad line 7780:

> 7778:             is_integral_type(Matcher::vector_element_basic_type(n)));
> 7779:   match(Set dst (VectorCastD2X src));
> 7780:   effect(KILL cr);

Remove effect.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/26919#discussion_r2301851424
PR Review Comment: https://git.openjdk.org/jdk/pull/26919#discussion_r2301845691
PR Review Comment: https://git.openjdk.org/jdk/pull/26919#discussion_r2301848959
PR Review Comment: https://git.openjdk.org/jdk/pull/26919#discussion_r2301846054