RFR: 8349764: RISC-V: C1: Improve Class.isInstance intrinsic [v2]

Wed Feb 12 16:38:48 UTC 2025

On Wed, 12 Feb 2025 12:01:46 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Update for Hamlin's comment
>
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 932:
> 
>> 930:         // Mirror: c_rarg0
>> 931:         // Object: c_rarg1
>> 932:         // Temps: x13, x14, x15, x16, x17
> 
> in this patch, maybe we should consistently use `c_rarg`n or `x1`n rather than mix these 2 types of register names?

Fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23551#discussion_r1953025047