RFR: 8349522: AArch64: Add backend implementation for new unsigned and saturating vector operations

[Bhavana Kilambi]

On Fri, 14 Feb 2025 06:23:49 GMT, Xiaohong Gong <xgong at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_vector.ad line 1574:
>> 
>>> 1572: instruct vsqadd_masked(vReg dst_src1, vReg src2, pRegGov pg) %{
>>> 1573:   predicate(UseSVE == 2 && !n->as_SaturatingVector()->is_unsigned());
>>> 1574:   match(Set dst_src1 (SaturatingAddV (Binary dst_src1 src2) pg));
>> 
>> for the masked match rules, should we also add `USE_DEF` effect for `dst_src1` to indicate that this register is both read and written to destructively ? I see that other similarly defined match rules in the ad file do not have this effect defined but I am wondering if this should be done?
>
> Hi @Bhavana-Kilambi , thanks for looking at this PR! And yes, the `dst_src1` should be `USE_DEF` actually, but I think it's safe not adding the effect here manually. The compiler adlc will add the use-def information for each operands when parsing each match rule. You may look at the code details from https://github.com/openjdk/jdk/blob/master/src/hotspot/share/adlc/formssel.cpp#L939 .

Thanks @XiaohongGong , got it :)

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PR Review Comment: https://git.openjdk.org/jdk/pull/23608#discussion_r1957863089