RFR: 8347489: RISC-V: Misaligned memory access with COH [v2]

[Fei Yang]

On Tue, 14 Jan 2025 09:56:18 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix assertions
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4466:
> 
>> 4464: 
>> 4465:       if (multi_block) {
>> 4466:         __ subi(consts, consts, vset_sew == Assembler::e32 ? 240 : 608);
> 
> makes the code less readable, maybe keep total_adds but keep the change of addi to subi ?

Sure. Fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23053#discussion_r1914619459