RFR: 8361353: [PPC64] C2: Add nodes UMulHiL, CmpUL3, UMinV, UMaxV, NegVI [v6]

[Richard Reingruber]

On Tue, 8 Jul 2025 11:47:28 GMT, David Briemann <dbriemann at openjdk.org> wrote:

>> src/hotspot/cpu/ppc/ppc.ad line 13601:
>> 
>>> 13599: instruct vneg4I_reg(vecX dst, vecX src) %{
>>> 13600:   match(Set dst (NegVI src));
>>> 13601:   predicate(PowerArchitecturePPC64 >= 9 && Matcher::vector_element_basic_type(n) == T_INT);
>> 
>> Why not also for `T_LONG` (using `vnegd`)?
>
> Because we have made the experience that the vector instructions for longs are very slow on PPC. So far all of them I tried or implemented were slower than the non-vectorized alternative.

Ok I remember that. Why have you implemented `VMINU` and `VMAXU` for `T_LONG` then?

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PR Review Comment: https://git.openjdk.org/jdk/pull/26115#discussion_r2192288024