RFR: 8348868: AArch64: Add backend support for SelectFromTwoVector [v15]

[Andrew Haley]

On Tue, 15 Jul 2025 11:28:17 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp line 2861:
>> 
>>> 2859:                                                      FloatRegister src2, FloatRegister index,
>>> 2860:                                                      FloatRegister tmp, unsigned vector_length_in_bytes) {
>>> 2861:   assert_different_registers(dst, src1, src2, tmp);
>> 
>> It seems `dst` can be the same with either `src1`, `src2`, or `tmp` from following implementation instruction, right? Maybe we should assert more accurate for different cases, such as `src2 == src1 + 1` when `vector_length_in_bytes == 16`?
>
> `dst, src1, src2` and `tmp` need to be different registers. Only `dst` and `index` can match depending on the type of the input. The reason why I didn't add `index` to the assertion.
> for the `src2 == src1 + 1` case, this is being checked in the definition of the `tbl` instruction for SVE in `src/hotspot/cpu/aarch64/assembler_aarch64.hpp` (but I realized it's not for Neon). Do you think it's enough if I make the Neon `tbl` instruction definition compatible with the SVE one? Or it's better to add a separate assertion here as well?

Just assert at the start of every function whatever that function needs.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23570#discussion_r2207321740