RFR: 8360654: AArch64: Remove redundant dmb from C1 compareAndSet [v2]

[Andrew Haley]

On Thu, 17 Jul 2025 14:27:23 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Samuel Chee has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Add back in dmb membar for non-LSE
>>   
>>   Change-Id: Ie64565420a1758d3191eaebed82c80584ce54ef6
>
> src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp line 1487:
> 
>> 1485:   if(!UseLSE) {
>> 1486:     __ membar(__ AnyAny);
>> 1487:   }
> 
> Suggestion:
> 
>   if(!UseLSE) {
>     // Prevent a later volatile load from being reordered with the STLXR in cmpxchg.
>     __ membar(__ StoreLoad);
>   }

I wonder if it might be a good idea to add a `trailingDMB` boolean argument to `cmpxchg` and `atomic_##NAME` instead.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26000#discussion_r2213522976