RFR: 8360654: AArch64: Remove redundant dmb from C1 compareAndSet [v2]

[Samuel Chee]

On Thu, 17 Jul 2025 14:31:18 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp line 1487:
>> 
>>> 1485:   if(!UseLSE) {
>>> 1486:     __ membar(__ AnyAny);
>>> 1487:   }
>> 
>> Suggestion:
>> 
>>   if(!UseLSE) {
>>     // Prevent a later volatile load from being reordered with the STLXR in cmpxchg.
>>     __ membar(__ StoreLoad);
>>   }
>
> I wonder if it might be a good idea to add a `trailingDMB` boolean argument to `cmpxchg` and `atomic_##NAME` instead.

@theRealAph coincidentally, I have been looking at `MacroAssembler::cmpxchgw` and `MacroAssembler::cmpxchgptr` recently, and it appears their trailing DMBs may also be unnecessary.

I have been unable to find any particular use patterns which relies on the existence of these trailing dmbs, so it does not seem necessary to add the trailingDMB option. Although would like to hear your thoughts on the issue.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26000#discussion_r2228158946