RFR: 8322174: RISC-V: C2 VectorizedHashCode RVV Version [v10]

[Fei Yang]

On Tue, 15 Jul 2025 14:05:25 GMT, Yuri Gaevsky <duke at openjdk.org> wrote:

>> The patch adds possibility to use RVV instructions for faster vectorizedHashCode calculations on RVV v1.0.0 capable hardware.
>> 
>> Testing: hotspot/jtreg/compiler/ under QEMU-8.1 with RVV v1.0.0.
>
> Yuri Gaevsky has updated the pull request incrementally with one additional commit since the last revision:
> 
>   - removed tail processing with RVV instructions as simple scalar loop provides in general better results

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2062:

> 2060:   vmv_s_x(v_powmax, pow31_highest);
> 2061: 
> 2062:   vsetvli(consumed, cnt, Assembler::e32, Assembler::m4);

What's the performance look like with a smaller `lmul` (m1 or m2)? I am asking this because there are hardwares there (like SG2044) with a VLEN of 128 instead of 256 like on K1.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17413#discussion_r2244179129