RFR: 8349582: APX NDD code generation for OpenJDK [v12]

[Emanuel Peter]

On Wed, 12 Mar 2025 20:52:07 GMT, Srinivas Vamsi Parasa <sparasa at openjdk.org> wrote:

>> The goal of this PR is to generate x86 code using Intel Advanced Performance Extensions (APX) instructions which doubles the number of general-purpose registers, from 16 to 32. Intel APX adds nondestructive destination (NDD) and no flags (NF) flavor for the scalar instructions through EVEX encoding.
>> 
>> For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>
> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
> 
>   undo changes to testing implementation

I had a quick look over this. It's a bit hard to review for me, because it is basically about specific APX instructions. We probably have to heavily rely on testing. But APX hardware is not yet available, right?

How can be  best test this? Is there any way to emulate, maybe using SDE? What testing did you run for this?

src/hotspot/cpu/x86/x86_64.ad line 6141:

> 6139:   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
> 6140: 
> 6141:   ins_cost(200); // XXX

What does the XXX stand for?

src/hotspot/cpu/x86/x86_64.ad line 6294:

> 6292: // Conditional move
> 6293: instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
> 6294: %{

Is this bracket usually not on the previous line?

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PR Review: https://git.openjdk.org/jdk/pull/23501#pullrequestreview-2680743351
PR Review Comment: https://git.openjdk.org/jdk/pull/23501#discussion_r1992899760
PR Review Comment: https://git.openjdk.org/jdk/pull/23501#discussion_r1992903548