RFR: 8355699: RISC-V: support SUADD/SADD/SUSUB/SSUB [v2]

[Hamlin Li]

On Mon, 5 May 2025 10:17:36 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   minor
>
> src/hotspot/cpu/riscv/riscv_v.ad line 696:
> 
>> 694:   match(Set dst_src (SaturatingAddV (Binary dst_src src1) v0));
>> 695:   ins_cost(VEC_COST);
>> 696:   format %{ "vsadd_masked $dst_src, $dst_src, $src1" %}
> 
> Nit: Seems the mask register (`v0`) is missing in opto asm for these masked operations.
> For integrity, we always print the mask register as the last operand for other masked nodes. 
> `format %{ "vsadd_masked $dst_src, $dst_src, $src1, $v0" %}`

Fixed. Thanks!

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PR Review Comment: https://git.openjdk.org/jdk/pull/25005#discussion_r2075049744