RFR: 8351950: C2: masked vector MIN/MAX AVX512: SIGFPE / no valid evex tuple_table entry

[Emanuel Peter]

On Sat, 3 May 2025 15:49:24 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> PR adds missing EVEX compressed displacement attributes used for computing the scale factor (N) of compressed displacement.
> AVX512 memory operand instructions use compressed disp8 encoding if the displacement is a multiple of scale (N), which depends on Vector Length, embedded broadcasting, and lane size.  Please refer to section 2.7.5 of Intel SDM for more details.
> 
> e.g., Consider two instructions, one with displacement 0x10203040 and the other with displacement 0x40, instruction operates over full 64-byte vector hence scale N = 64. Displacement of latter instruction is a multiple of scale, thus can be represented by 1 byte displacement encoding, while the former requires 4 bytes to represent displacement in instruction encoding.
> 
> 
> 1) vpternlogq $0xff,0x10203040(%r20,%r21,8),%zmm23,%zmm24
>     EVEX        OP   MR   SIB       DISP       IMM
> --------------|----|----|----|---------------|-----|
> 62 6b c1 40     25   84   ec     40 30 20 10     ff
> 
> 2) vpternlogq $0xff,0x40(%r20,%r21,8),%zmm23,%zmm24
> For full vector width operation, scalar matches with vector size, hence scale N = 64
> effective displacement / compressed DISP8 = OFFSET(64) / 64 = 0x1 
>     EVEX       OP   MR SIB    DISP     IMM
> -------------|----|---|---|-----------|---|
> 62 6b c1 40    25  44   ec      01     ff 
> 
> 
> Kindly review and share your feedback.
> 
> Best Regards,
> Jatin

@jatin-bhateja Thanks you for looking into this!

The fix looks generally reasonable, thanks for adding all the tests!

src/hotspot/cpu/x86/assembler_x86.cpp line 11542:

> 11540:   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
> 11541:   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
> 11542:   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_NObit);

@jatin-bhateja How is this `fma` case related to the `min / max` cases that were reported? I did also not find a test below.

src/hotspot/cpu/x86/assembler_x86.cpp line 11571:

> 11569:   attributes.set_is_evex_instruction();
> 11570:   attributes.set_embedded_opmask_register_specifier(mask);
> 11571:   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);

@jatin-bhateja How are these `perm` cases related to the `min / max` cases that were reported? I did also not find a test below.

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PR Review: https://git.openjdk.org/jdk/pull/25021#pullrequestreview-2818982572
PR Review Comment: https://git.openjdk.org/jdk/pull/25021#discussion_r2075881555
PR Review Comment: https://git.openjdk.org/jdk/pull/25021#discussion_r2075882162