RFR: 8351994: Enable Extended EVEX to REX2/REX demotion when src and dst are the same [v21]

[Jatin Bhateja]

On Wed, 7 May 2025 19:00:59 GMT, Srinivas Vamsi Parasa <sparasa at openjdk.org> wrote:

>> Intel APX NDD instructions are encoded using EVEX encoding. The goal of this PR is to enable optimized instruction encoding for Intel APX NDD instructions when the non-destructive destination is same as the first source.
>> 
>> For example:
>> 
>> `eaddl r18, r18, r25` can be encoded as `addl r18, r25` using APX REX2 encoding
>> `eaddl r2, r2, r7` can be encoded as `addl r2, r7` using non-APX legacy encoding
>
> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
> 
>   eimull revert fully to original version

src/hotspot/cpu/x86/assembler_x86.cpp line 2517:

> 2515: 
> 2516: void Assembler::eimull(Register dst, Register src1, Register src2, bool no_flags) {
> 2517:   evex_opcode_prefix_and_encode_swap(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, EVEX_32bit, 0xAF, no_flags, true /* is_map1 */);

Suggestion:

  evex_opcode_prefix_and_encode_swap(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0xAF, no_flags, true /* is_map1 */);

src/hotspot/cpu/x86/assembler_x86.cpp line 4068:

> 4066: void Assembler::enegl(Register dst, Register src, bool no_flags) {
> 4067:   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
> 4068:   int encode = evex_prefix_and_encode_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);

Since VEX_OPCODE_OF_3C is not a standard MAP4 encoding please add /* MAP4 */ after it in the places.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2089247442
PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2089250955