RFR: 8351994: Enable Extended EVEX to REX2/REX demotion when src and dst are the same [v27]

[Jatin Bhateja]

On Sun, 18 May 2025 01:04:45 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Update x86-asmtest.py to enable demotion by default and make test generation optional
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 6809:
> 
>> 6807: 
>> 6808: void Assembler::eshldl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) {
>> 6809:   evex_opcode_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), imm8, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0xA4, no_flags, true /* is_map1 */);
> 
> Here the opcode is set to 0xA4 which is correct for demotion case, in case we don't demote then opcode is 0x24.  This is only relevant to NDD flavours of shldl/shldq with imm8 shift values. I will suggest adding a comment here giving clear explanation as it not intiutive at first glance and manul clearly specify 0x24 as the opcode.

Better idea to pass 0x24 opcode from the top level which is what manual says and do the appropriate adjustments by oring with 0x80 if we demote it to REX2 / REX prefixed instruction

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PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2094296930