RFR: 8351994: Enable Extended EVEX to REX2/REX demotion when src and dst are the same [v27]

[Srinivas Vamsi Parasa]

On Sun, 18 May 2025 01:27:31 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Update x86-asmtest.py to enable demotion by default and make test generation optional
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 12973:
> 
>> 12971: }
>> 12972: 
>> 12973: void Assembler::evex_opcode_prefix_and_encode_swap(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
> 
> Can we also not unify this one with evex_opcode_prefix_and_encode by passing additional swap argument

The two separate functions were unified in the updated code.

> src/hotspot/cpu/x86/assembler_x86.cpp line 12991:
> 
>> 12989: 
>> 12990: int Assembler::evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
>> 12991:                                           InstructionAttr *attributes, bool no_flags, bool use_prefixq) {
> 
> evex_prefix_and_encode_ndd => emit_eevex_prefix_or_demote_ndd
> 
> Naming suggestion.

Changed as suggested in the updated code.

> src/hotspot/cpu/x86/assembler_x86.cpp line 13024:
> 
>> 13022: }
>> 13023: 
>> 13024: void Assembler::evex_prefix_arith(Register dst, Register nds, int32_t imm32, VexSimdPrefix pre, VexOpcode opc,
> 
> Suggestion:
> 
> void Assembler::emit_eevex_prefix_or_demote_arith_ndd(Register dst, Register nds, int32_t imm32, VexSimdPrefix pre, VexOpcode opc,

Please see this renaming suggestion incorporated into the latest update.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2098846041
PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2098845187
PR Review Comment: https://git.openjdk.org/jdk/pull/24431#discussion_r2098844309