RFR: 8357056: RISC-V: Asm fixes - load/store width [v2]

[Feilong Jiang]

On Tue, 20 May 2025 12:02:43 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi, please consider.
>> 
>> While working on https://github.com/openjdk/jdk/pull/25252, I notice:
>> - Major op code was just repeat
>> - Width coded in binary
>> - Stores have mixed up rs1 and rs2
>> - Bonus, fsd used a macro for no reason
>> 
>> I think this improves readability.
>> 
>> Tested tier1
>> 
>> Thanks, Robbin
>
> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision:
> 
>  - Fixed flh/flw/fld
>  - Merge branch 'master' into asm_fixes
>  - Fixes

Overall looks good! With one minor suggestion!

src/hotspot/cpu/riscv/assembler_riscv.hpp line 3307:

> 3305: 
> 3306: // --------------------------
> 3307:   void sd(Register Rd, Register Rs, const int32_t offset) {

We can rename `Rd`/`Rs` to `Rs2`/`Rs1` to be more consistent with the specification.

src/hotspot/cpu/riscv/assembler_riscv.hpp line 3322:

> 3320: 
> 3321: // --------------------------
> 3322:   void sw(Register Rd, Register Rs, const int32_t offset) {

Same here.

src/hotspot/cpu/riscv/assembler_riscv.hpp line 3337:

> 3335: 
> 3336: // --------------------------
> 3337:   void fsd(FloatRegister Rd, Register Rs, const int32_t offset) {

And here.

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PR Review: https://git.openjdk.org/jdk/pull/25253#pullrequestreview-2856821785
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2099704221
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2099704656
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2099707612