RFR: 8351950: C2: AVX512 vector assembler routines causing SIGFPE / no valid evex tuple_table entry [v5]

[Sandhya Viswanathan]

On Wed, 21 May 2025 01:57:35 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> PR adds missing EVEX compressed displacement attributes used for computing the scale factor (N) of compressed displacement.
>> AVX512 memory operand instructions use compressed disp8 encoding if the displacement is a multiple of scale (N), which depends on Vector Length, embedded broadcasting, and lane size.  Please refer to section 2.7.5 of Intel SDM for more details.
>> 
>> e.g., Consider two instructions, one with displacement 0x10203040 and the other with displacement 0x40, instruction operates over full 64-byte vector hence scale N = 64. Displacement of latter instruction is a multiple of scale, thus can be represented by 1 byte displacement encoding, while the former requires 4 bytes to represent displacement in instruction encoding.
>> 
>> 
>> 1) vpternlogq $0xff,0x10203040(%r20,%r21,8),%zmm23,%zmm24
>>     EVEX        OP   MR   SIB       DISP       IMM
>> --------------|----|----|----|---------------|-----|
>> 62 6b c1 40     25   84   ec     40 30 20 10     ff
>> 
>> 2) vpternlogq $0xff,0x40(%r20,%r21,8),%zmm23,%zmm24
>> For full vector width operation, scalar matches with vector size, hence scale N = 64
>> effective displacement / compressed DISP8 = OFFSET(64) / 64 = 0x1 
>>     EVEX       OP   MR SIB    DISP     IMM
>> -------------|----|---|---|-----------|---|
>> 62 6b c1 40    25  44   ec      01     ff 
>> 
>> 
>> Kindly review and share your feedback.
>> 
>> Best Regards,
>> Jatin
>
> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review Resoultions

Looks good to me. Thanks for fixing this issue.

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Marked as reviewed by sviswanathan (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/25021#pullrequestreview-2858346557