RFR: 8365732: RISC-V: implement AES CTR intrinsics [v15]

[Anjian Wen]

On Mon, 3 Nov 2025 03:07:01 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Anjian Wen has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   modify some var names
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2623:
> 
>> 2621:     __ rev8(tmp1, tmp1);
>> 2622:     __ sd(tmp1, Address(counter));
>> 2623:   }
> 
> Can you add some code comment and maybe assertions about the input registers? Like:
> 
>   // Big-endian 128-bit + 64-bit -> 128-bit addition.
>   void be_inc_counter_128(Register counter, Register tmp1, Register tmp2) {
>     assert_different_registers(counter, tmp1, tmp2, t0);
>     __ ld(tmp1, Address(counter, 8)); // Load 128-bits from counter
>     __ ld(tmp2, Address(counter));
>     __ rev8(tmp1, tmp1);              // Convert big-endian to little-endian
>     __ rev8(tmp2, tmp2);
>     __ addi(tmp1, tmp1, 1);
>     __ seqz(t0, tmp1);                // Check for result overflow
>     __ add(tmp2, tmp2, t0);           // Add 1 if overflow otherwise 0
>     __ rev8(tmp1, tmp1);              // Convert little-endian to big-endian
>     __ rev8(tmp2, tmp2);
>     __ sd(tmp1, Address(counter, 8)); // Store 128-bits to counter
>     __ sd(tmp2, Address(counter));
>   }
> 
> 
> PS: My local test show that this test "com/sun/crypto/provider/Cipher/AEAD/AEADBufferTest.java" is failing with this change. We need to resolve that.

thanks, I have fixed it

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2505912451