RFR: 8365732: RISC-V: implement AES CTR intrinsics [v26]

[Anjian Wen]

On Tue, 18 Nov 2025 18:23:33 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Anjian Wen has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   modify stub_id name
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2748:
> 
>> 2746:     };
>> 2747: 
>> 2748:     __ vsetivli(x0, 4, Assembler::e32, Assembler::m1);
> 
> A general question, can we make it bigger than `4`, or even `m2`?

This is a good question! I spent a relatively long time on it earlier. 
Initially, I tried m2 and m4. In the case of m4, I had already developed a version passed all the test(which really take a long time to test), it seems faster, but since the Java API supports non-complete block data encrypt or decrypt, it is difficult to ensure the time for counter increment is consistent under various circumstances, which may pose a security risk thanks to the remind of Andrew. Additionally, the Java API allows the counter to grow up to 128 bits, RV does not have a very suitable vector 128-bit add currently. Using other types such as 64-bit requires consideration of the overflow issue, and using a version higher than m1 makes it more harder to ensure the time for each counter increment. Based on these considerations, I selected m1.

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2540859234