RFR: 8351016: RA support for EVEX to REX/REX2 demotion to optimize NDD instructions [v13]

[Vladimir Ivanov]

On Wed, 19 Nov 2025 18:12:22 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Currently, while choosing the colour (register) for a definition live range during the select phase of register allocation, we pick the first available colour that does not match with already allocated neighboring live ranges.
>> 
>> With Intel APX NDD ISA extension, several existing two-address arithmetic instructions can now have an explicit non-destructive destination operand; this, in general, saves additional spills for two-address instructions where the destination is also the first source operand, and where the source live range surpasses the current instruction.
>> 
>> All NDD instructions mandate extended EVEX encoding with a bulky 4-byte prefix, [JDK-8351994](https://github.com/openjdk/jdk/pull/24431) added logic for NDD to REX/REX2 demotion in the assembler layer, but due to the existing first color selection register allocation policy, the demotions are rare. This patch biases the allocation of NDD definition to the first source operand or the second source operand for the commutative class of operations.
>> 
>> Biasing is a compile-time hint to the allocator and is different from live range coalescing (aggressive/conservative), which merges the two live ranges using the union find algorithm.  Given that REX encoding needs a 1-byte prefix and REX2 encoding needs a 2-byte prefix, domotion saves considerable JIT code size.
>> 
>> The patch shows around 5-20% improvement in code size by facilitating NDD demotion.
>> 
>> For the following micro, the method JIT code size reduced from 136 to 120 bytes, which is around a 13% reduction in code size footprint.
>>  
>> **Micro:-**
>> <img width="900" height="300" alt="image" src="https://github.com/user-attachments/assets/9cbe9da8-d6af-4b1c-bb55-3e5d86eb2cf9" />
>> 
>> 
>> **Baseline :-**
>> <img width="900" height="300" alt="image" src="https://github.com/user-attachments/assets/ff5d50c6-fdfa-40e8-b93d-5f117d5a1ac6" />
>> 
>> **With opt:-**
>> <img width="900" height="300" alt="image" src="https://github.com/user-attachments/assets/bff425b0-f7bf-4ffd-a43d-18bdeb36b000" />
>> 
>> Thorough validations are underway using the latest [Intel Software Development Emulator version 9.58](https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html).
>> 
>> Kindly review and share your feedback.
>> 
>> Best Regards,
>> Jatin
>
> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review comments resolution

src/hotspot/cpu/x86/x86.ad line 2649:

> 2647:   }
> 2648: 
> 2649:   // First operand of MachNode corresponding to Intel APX NDD selection

Very informative comments! Thank you.

I suggest to shape it as follows:

if ((mdef->flags() & Node::PD::Flag_ndd_demotable) != 0) {
  switch (oper_index) {
    // First operand of MachNode corresponding to Intel APX NDD selection
    // pattern can share its assigned register with definition operand if
    // their live ranges do not overlap, in such a scenario we can demote
    // it to legacy map0/map1 instruction by replacing its 4-byte extended
    // EVEX prefix with shorter REX/REX2 encoding. Demotion candidates
    // are decorated with a special flag by instruction selector.
    case 1: return true;

    // For commutative operation allocation of definition
    // operand can also be biased towards second operand.
    case 2: return (mdef->flags() & Node::PD::Flag_ndd_commutative) != 0);

    // No register biasing supported for other operands.
    default: return false;
  }
}

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/26283#discussion_r2547714121