RFR: 8364305: Support AVX10 saturating floating point conversion instructions [v3]

[Jatin Bhateja]

On Fri, 29 Aug 2025 23:46:18 GMT, Mohamed Issa <missa at openjdk.org> wrote:

>> Intel® AVX10 ISA [1] extensions added new saturating floating point conversion instructions which comply with definitions in section 5.8 of the 2019 IEEE-754 standard. They can compute floating point to integral type conversions while also handling special inputs such as NaN, +Infinity, and -Infinity.
>> 
>> Without AVX10.2, the current approach starts by converting the floating point value(s) in the source register to the desired integral value(s) in the destination register. In the scalar case, the CVTTSS2SI (single precision) or CVTTSD2SI (double precision) instruction is used. In the vector case, the CVTTPS2DQ (single precision) or CVTTPD2DQ (double precision) is used. However, if the source contains a special value (NaN, -Infinity, +Infinity, <= Integer.MIN_VALUE, or >= Integer.MAX_VALUE), extra handling is required. The specific sequence of instructions involved depends on the source (single precision vs double precision), destination (long, integer, short, or byte), level of parallelization (scalar vs vector), and supported AVX extension type. Essentially though, the special values are mapped to values (NaN -> 0, -Infinity, <= Integer.MIN_VALUE -> Integer.MIN_VALUE, +Infinity, >= Integer.MAX_VALUE -> Integer.MAX_VALUE) in the integer range with the help of a few temporary regis
 ters to store intermediate results.
>> 
>> This change uses the new AVX10.2 scalar (VCVTTSS2SIS or  VCVTTSD2SIS) and vector (VCVTTPS2QQS, VCVTTPS2DQS, VCVTTPD2QQS, and VCVTTPD2DQS) instructions on supported platforms to avoid the extra handling described above. Also, the JTREG tests listed below were used to verify correctness with `-XX:-UseSuperWord` / `-XX:+UseSuperWord` options to exercise both scalar and vector paths. The baseline build used is [OpenJDK v26-b11](https://github.com/openjdk/jdk/releases/tag/jdk-26%2B11).
>> 
>> 1. `jtreg:test/hotspot/jtreg/compiler/codegen/TestByteDoubleVect.java`
>> 2. `jtreg:test/hotspot/jtreg/compiler/codegen/TestByteFloatVect.java`
>> 3. `jtreg:test/hotspot/jtreg/compiler/codegen/TestIntDoubleVect.java`
>> 4. `jtreg:test/hotspot/jtreg/compiler/codegen/TestIntFloatVect.java`
>> 5. `jtreg:test/hotspot/jtreg/compiler/codegen/TestLongDoubleVect.java`
>> 6. `jtreg:test/hotspot/jtreg/compiler/codegen/TestLongFloatVect.java`
>> 7. `jtreg:test/hotspot/jtreg/compiler/codegen/TestShortDoubleVect.java`
>> 8. `jtreg:test/hotspot/jtreg/compiler/codegen/TestShortFloatVect.java`
>> 
>> [1] https://www.intel.com/content/www/us/en/content-details/856721/intel-adv...
>
> Mohamed Issa has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix input size enum values for AVX 10.2 conversion instructions that take memory as the source

src/hotspot/cpu/x86/x86.ad line 7804:

> 7802:   predicate(VM_Version::supports_avx10_2() &&
> 7803:             is_integral_type(Matcher::vector_element_basic_type(n)));
> 7804:   match(Set dst (VectorCastD2X src));

I assume your intent here is to feed the memory operand to the vector cast IR, a memory operand is first loaded into register using LoadVector IR, so a CISC / memory variant of pattern should consume the Load IR such that the operand is directly exposed to the instruction. Checkout https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/x86/x86.ad#L8986

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PR Review Comment: https://git.openjdk.org/jdk/pull/26919#discussion_r2313165676