RFR: 8365926: RISC-V: Performance regression in renaissance (chi-square) [v2]

[Fei Yang]

On Mon, 1 Sep 2025 14:42:47 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/nativeInst_riscv.cpp line 111:
>> 
>>> 109:   if (mt_safe) {
>>> 110:     OrderAccess::release();
>>> 111:     ICache::invalidate_range(jal_pc, NativeInstruction::instruction_size);
>> 
>> should `jal_pc` be `instruction_address()`?
>
> We have:
> 
> auipc // instruction_address()                                                                                     # Never changed
> ld       // instruction_address() + NativeInstruction::instruction_size                    # Never changed
> jal(r)  // instruction_address() + 2 * NativeInstruction::instruction_size (jal_pc) # jal<->jalr
> 
> We only change the instruction at "instruction_address() + 2 * NativeInstruction::instruction_size".
> 
> Note that jal_pos and jal_pc means a "jump and link instruction", not specifically jal or jalr.
> 
> Make sense?

Maybe we can give it a new name to avoid possible confusion? `jmp_pc` or simply `pc`?

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PR Review Comment: https://git.openjdk.org/jdk/pull/26944#discussion_r2314762084