RFR: 8365732: RISC-V: implement AES CTR intrinsics [v7]

[Anjian Wen]

On Fri, 25 Jul 2025 10:22:49 GMT, Anjian Wen <wenanjian at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2745:
>> 
>>> 2743:     __ vsetivli(x0, 4, Assembler::e32, Assembler::m1);
>>> 2744:     __ vrev8_v(v31, v31, Assembler::VectorMask::v0_t); // convert big-endien to little-endian
>>> 2745:     __ vadd_vi(v31, v31, 1, Assembler::VectorMask::v0_t);
>> 
>> Are you sure this is correct? See `com.sun.crypto.provider.CounterMode::increment`.
>
> Thanks for the review. I'm still developing it.
> Regarding the growth of the counter array, it should use 8 bytes to store the count.  I use 4 Byte here according to OpenSSL aes-ctr code, I will try to fix it later
> https://github.com/openssl/openssl/blob/master/crypto/aes/asm/aes-riscv64-zvkb-zvkned.pl#L242

> Are you sure this is correct? See `com.sun.crypto.provider.CounterMode::increment`.

Hi @theRealAph , according to your advice and code from `com.sun.crypto.provider.CounterMode::increment`,  I have modified my patch about counter increase by increasing 2 8Byte. Most of case increasing the first 8 Byte(from 8bit to 15 bit) is enough, it only needs to increase the next 8Byte when the first 8Byte overflows. And I have added a test for limit case, could you please help review again?

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2343365699