RFR: 8359378: aarch64: crash when using -XX:+UseFPUForSpilling

[Boris Ulasevich]

On Thu, 18 Sep 2025 07:03:52 GMT, Roberto Castañeda Lozano <rcastanedalo at openjdk.org> wrote:

>> AArch64 BarrierSetAssembler path assumes only FP/vector ideal regs reach the FP spill/restore encoding. With -XX:+UseFPUForSpilling Register Allocator may allocate scalar values in FP registers. When such values (Op_RegI/Op_RegN/Op_RegL/Op_RegP) hit `BarrierSetAssembler::encode_float_vector_register_size`, we trip ShouldNotReachHere in release build and **"unexpected ideal register"** assertion in debug build.
>> 
>> Fix: teach the encoder to handle scalar ideal regs when they physically live in FP regs:
>> - treat Op_RegI / Op_RegN as 32-bit (single slot) - same class as Op_RegF
>> - treat Op_RegL / Op_RegP as 64-bit (two slots) - same class as Op_RegD
>> 
>> Related:
>> - reproduced since #19746
>> - spilling logic: 
>>   - #18967
>>   - #17977
>> 
>> Testing: tier1-3 with javaoptions -Xcomp -Xbatch -XX:+UseFPUForSpilling on AARCH
>
> Hi @bulasevich, thanks for working on this issue, but please note that it was already assigned to me ([JDK-8359378](https://bugs.openjdk.org/browse/JDK-8359378)). I am fine with re-assigning it to you, but [next time please ask first, to avoid work duplication](https://openjdk.org/guide/#i-found-an-issue-in-jbs-that-i-want-to-fix).

Right, @robcasloz,
I started investigating this issue thinking it was something wrong in my own code. Once I realized it was a common issue already assigned, I decided to propose a fix since it looked a bit abandoned. I didn’t mean to bypass your work -- you’re right, I should have contacted you first.
Anyway, I’d appreciate your review. Do you think my change is reasonable? If not, let me close this PR and leave it to you.

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PR Comment: https://git.openjdk.org/jdk/pull/27350#issuecomment-3306764696