jdk and NUMA

[Charlie Hunt]

In general, best practice .... use +UseNUMA when the jvm you are launching will span more than one memory node.

Charlie 

David Dabbs <dmdabbs at gmail.com> wrote:

>Thank you ramki, for the reply.
>
>What "issues" should might one expect after adding +UseNUMA?
>
>
>
>
>-----Original Message-----
>From: Y. S. Ramakrishna [mailto: @oracle.com] 
>Sent: Thursday, September 09, 2010 5:31 PM
>To: David Dabbs
>Subject: Re: jdk and NUMA
>
>Yes, just use +UseNUMA to begin with, and let us know if there are
>any issues.
>
>-- ramki
>
>On 09/09/10 12:04, David Dabbs wrote:
>> My apologies if this is not the correct place for this question.
>> 
>> I have a shiny new NUMA-capable Xeon server and want to ensure that my
>Java
>> app(s) make full use of the hardware.
>> So, I ran java (jdk 6u21) -XX:+PrintFlagsFinal and (naively) expected to
>see
>> UseNUMA := true but did not.
>> 
>> I found this post
>> 
>> http://blogs.sun.com/jonthecollector/entry/help_for_the_numa_weary
>> 
>> If its simply a matter of turning it on that's what I'll do. Any
>guidelines
>> about use of mumactl or the jdks NUMA "knobs"?
>> 
>> 
>> uname -a
>> Linux 2.6.18-128.7.1.el5 #1 SMP Mon Aug 24 08:21:56 EDT 2009 x86_64 x86_64
>> x86_64 GNU/Linux
>> 
>> Linux, CentOS 5
>> 
>> 
>> cat /proc/cpuinfo
>> 
>> processor       : 0
>> vendor_id       : GenuineIntel
>> cpu family      : 6
>> model           : 26
>> model name      : Intel(R) Xeon(R) CPU           E5530  @ 2.40GHz
>> stepping        : 5
>> cpu MHz         : 2394.112
>> cache size      : 8192 KB
>> physical id     : 1
>> siblings        : 8
>> core id         : 0
>> cpu cores       : 4
>> apicid          : 16
>> fpu             : yes
>> fpu_exception   : yes
>> cpuid level     : 11
>> wp              : yes
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
>> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx
>rdtscp
>> lm constant_tsc ida nonstop_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr
>> popcnt lahf_lm
>> bogomips        : 4791.64
>> clflush size    : 64
>> cache_alignment : 64
>> address sizes   : 40 bits physical, 48 bits virtual
>> power management: [8]        
>> 
>> This repeats for processors 1-15.
>> 
>> Two physical ids, 0,1.
>> 
>> 
>> 
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