CPU-feature detection is broken for new Fujitsu Sparc64-X CPUs

[Volker Simonis]

On Wednesday, November 27, 2013, Vladimir Kozlov wrote:

> >>>     if (is_niagara() || (is_sun4v() && is_sparc64())) {
> > So I think the above check is the best I can currently do. But I will be
> > happy to change it once we get new informations.
>
> I think we should simple use has_blk_init() check to guard UseMemSetInBOT
> setting.
>
>
Yes, that's good!


> Regards,
> Vladimir
>
> On 11/27/13 12:43 PM, Volker Simonis wrote:
>
> On Wednesday, November 27, 2013, Vladimir Kozlov wrote:
>
>  On 11/27/13 10:02 AM, Volker Simonis wrote:
>
>  Hi Vladimir,
>
> thanks a lot for commenting on this issue in the bug report.
>
>
> - Regarding 'UseMemSetInBOT' I agree that we should know how memset() is
> implemented on Solaris/Fujitsu Sparc-X and/or how BIS is working on
> Fujitsu
> Sparc-X. Could you please find this out. I don't see how I could get this
> information:(
>
>
> I will try :)
>
>
>  But in order to be on the safe side, I think we should reset
> UseMemSetInBOT
> until then:
>
>     if (is_niagara() || (is_sun4v() && is_sparc64())) {
>       // When using CMS or G1, we cannot use memset() in BOT updates
>       // because the sun4v/CMT version in libc_psr uses BIS which
>       // exposes "phantom zeros" to concurrent readers. See 6948537.
>       if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC ||
> UseG1GC))
> {
>         FLAG_SET_DEFAULT(UseMemSetInBOT, false);
>       }
>
> Currently, this is not done, that's why the second assertion fires. But
> you
> don't see it in a product build and this really bothers me most because I
> don't want to run into these problems on new Fujitsu machines. What do you
> think?
>
>
> Totally agree. Why you need 'is_sun4v() &&' ? Can we have sparc64 which
> are not sun4v?
>
>
>
> Actually I simply don't know. From Wikipedia (
> http://en.wikipedia.org/wiki/SPARC64_VI) I read that there exist Sparc64
> V,
> VI, VII, VIII, IX and X, but I don't know which of them is the first that
> implemented sun4v. We only recently got a Sparc64-X so that's the only one
> I can actually look at.
>
> So I think the above check is the best I can currently do. But I will be
> happy to change it once we get new informations.
>
>
>    - Regarding 'is_niagara(int features)', would it be fine if I'd change:
>
>
> static bool is_niagara(int features)  { return (features & sun4v_m) != 0;
> }
>
> to:
>
> static bool is_niagara(int features)  { return (features & sun4v_m) != 0
> &&
> (features & sparc64_family_m) == 0; }
>
>
> I prefer this change. Add comment that sun4v_m is true on both.
>
>
>
> OK, I'll prepare a webrev.
>
>
>
>
>  With this change, I could leave the assertion:
>
>     assert((is_T_family(features) == is_niagara(features)), "Niagara should
> be T series");
>
> untouched and it would work on both, Oracle and Fujitsu CPUs.
>
> On the other hand, maybe it would be clearer to remove
> is_niagara(features)
> altogether and replace create two new function:
>
>     static bool is_sparc64(int features)              { return (features &
> sparc64_family_m) != 0; }
>     static bool is_sun4v(int features)                { return (features &
> sun4v_m) != 0; }
>
> Then we could change the assertion to:
>
>     assert((is_T_family(features) == is_sun4v(features) ||
> is_sparc64(features)), "Niagara should be T series");
>
> What do you think?
>
>
>
> - Regarding UseBlockCopy and UseBlockZeroing: what do you mean by "'block
> init instructions' could be implemented differently on Fujitsu Sparc-X"?
> Currently we only check 'has_block_zeroing()' for both options, but
> 'has_block_zeroing()' only returns true on T4. On the other hand, Fujitsu
> Sparc64-X supports the 'blk_init' extension - it's just not clear if it
> works like for T1/T2 or like for T4. So depending on this answer we should
> change 'has_block_zeroing()' to also work correctly on Sparc64-X, right?
>
>
> BIS was since T1. But T4 implementation of BIS instructions GUARANTEE
> zeroing of cacheline before storing value (STXA) without fetching data from
> memory. It is used onl
>
>