More on memory barriers
dl at cs.oswego.edu
Tue Sep 16 10:44:42 UTC 2014
On 09/16/2014 03:38 AM, Andrew Haley wrote:
> On 15/09/14 20:44, Dean Long wrote:
>> If volatile store uses AArch64 "stlr" and volatile load uses "ldar",
>> then is that enough (no additional barriers, including StoreLoad,
>> required)? That's my understanding from the comments in
>> orderAccess.hpp regarding ia64 st.rel and ld.acq.
> Not quite: we'd still need a StoreLoad even after a stlr.
Not always. The cookbook conservatively approximates JMM rules.
But maybe in practice you do because...
> I don't think I can use stlr without making changes to C2.
... in particular, a better way of handling fused access+fence
instructions, which looks to be useful across several
processors (even x86).
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